Hi HN,

I ported the teaching OS xv6-riscv to HiFive Unmatched and got it running on real hardware, including passing usertests.

I've been self-studying OS internals using the MIT 6.1810 materials. After finishing most of the labs, I was eager to see what it's like to run the OS on bare metal, rather than QEMU.

The Unmatched may not have the latest RISC-V features, but it's well-documented, and the Rev B release has made it more affordable, which makes it a good learning platform.

The porting process involved several interesting challenges:

- Hardware Quirks: Handling things like enabling A/D bits in PTEs (the hardware doesn't set them automatically, causing page faults), proper handling of interrupts, and instruction cache synchronization.

- Boot Flow: xv6 expects M-mode on startup, but standard RISC-V boot flows (typically via OpenSBI) jump to S-mode. To bridge this gap, I created a minimal U-Boot FIT image that contains only the xv6 kernel. This way, U-Boot SPL handles the complex CPU/DDR initialization, then hands control to xv6 in M-mode (skipping OpenSBI).

- Drivers: Ported an SPI SD card driver, replacing the virtio disk driver.

I wrote up implementation notes here: https://github.com/eyengin/xv6-riscv-unmatched/blob/unmatche...

Hopefully, this is useful for others who are learning OS internals and want to try running their code on real RISC-V hardware.