The thing I love about blog posts like these is how it reminds me that the tech world is a vast ocean that encompasses so many disciplines; it's not all full stack web development.
Related: I did not understand 95% of what she wrote.
On some of my cover letters I wrote "full stack from the transistors upwards", because at one point or another I have shipped code in:
- IC design software (at a startup bought by Cadence)
- an IC (contract out of Dallas semi)
- FPGA HFT acceleration
- fixing some OS drivers for Windows CE
- finding a compiler bug
- various bits of embedded firmware in C and assembly for various platforms
- debugging with a scope
- desktop applications
- a web server (defunct ZWS)
- web apps (Perl. Long time ago)
Somehow I've never written a react app.
> Somehow I've never written a react app.
Count your blessings.
lol
I wrote here a couple days ago: "For a Hacker News degenerate, everything in the world revolves around bean-counting B2B SaaS CRUD crapps, but it doesn't mean it's all there is to the world, right?"
I didn't even know that 180nm was still a thing but clearly it is because apparently the cost difference is like USD 100M for 180nm vs USD 10B or more for the latest tech?
Is it true that we will likely have these 180nm chips for things like light bulbs for the foreseeable future?
Yes, actually 180 nm still represents a sizable amount of the market, in terms of volume! In more niche applications where chips contain lots of analog functionlity, you can still find plenty of designs being done in 180, 130, 110, and 65 nm. Most corporate designs don't disclose this, but I'd venture to guess the majority of integrated circuits in your home are made on these larger "process nodes". I work in 65nm and 130nm, for example. Free to ask if you want to know more!
I work in a similar market, and we're only just starting to phase out these larger nodes and move to 22nm simply for wafer availability.
It doesn't benefit from 22nm - analog blocks generally don't scale down at all, they have to be a particular size to achieve particular current handling, inductance etc. requirements. But we need the production line availability.
I'm not OP, but perhaps you, or somebody else here, could answer my question, albeit one that is slightly off-topic. In the recent years, in part courtesy of cryptoindustry investment, there were many advancements in zero-knowledge mathematics and applied cryptography. I've been on-and-off researching computational approaches to liquid democracy[1], on the off-chance that we may one day apply it in my country, Ukraine, and I came to conclusion that open hardware-as-public good are table stakes to that end. The modern computers are way too complex, and the trust in them is at an all-time low. To bring computation into politics—it's a tall order. However, if we could buy a fab, design some hardware transparently, allow inspections from civil groups and scientists, maybe that could work... What kind of costs are we looking at for establishing something like 130nm process, and would it be possible to buy out the necessary IP, too, so that everything could be done in the open?
Does this even work longterm? I'd like to think transparent-by-design hardware manufacturing is not a pipe dream, but if that's the case, I would hate to give it too much thought.
Hey, I'm not a system-level digital designer, but for government-level initiatives to provide 130nm and 65nm fabs for public benefit, yes it exists!
From the 2025 Free Silicon Conference:
https://wiki.f-si.org/index.php?title=The_Transparent_Refere...
https://wiki.f-si.org/images/e/eb/OpenFab%40FSiC2025.pdf
The initiative started in Germany, where the research institute IHP already provides an open source 130nm PDK and associated foundry, but interest is spreading. Here's the abstract from that talk:
"The European Chips Act aims to double Europe’s share in global semiconductor manufacturing to 20% by 2030. However, most current investments focus on leading-edge nodes and pilot lines, which – while important – are not sufficient to achieve broad capacity scaling. At the same time, demand for mature nodes (≥65 nm) remains strong: over two-thirds of chips in automotive and industrial sectors still rely on nodes ≥90 nm, and this trend is expected to persist through 2030. This contribution introduces the concept of a Transparent Reference Fab – a fully open, scalable semiconductor fabrication model designed to serve as a blueprint for sovereign and trustworthy chip manufacturing in Europe. Unlike traditional pilot lines, the Transparent Reference Fab is production-ready and replicable. It includes open access to process design kits (PDKs), equipment configurations, process recipes, and operational know-how. The fab targets mature nodes, especially 65 nm CMOS, and is intended to be built on existing infrastructure to reduce time-to-market and technical risk. We argue that such a model can significantly multiply Europe’s production capacity by enabling private and public actors to replicate the reference fab across regions. This approach would not only strengthen Europe’s position in strategic semiconductor supply chains but also foster innovation, education, and security through transparency. The paper presents the strategic rationale, technical architecture, and implementation path, positioning the Transparent Reference Fab as a critical instrument for European resilience and competitiveness."
Wow, thanks! I was completely unaware of it, of course.
This project exists, here it is: https://opentitan.org/
I previously came across OpenTitan, but it's hardware design only, right? It doesn't actually concern itself with bringing up transparent manufacturing process?
For example, I couldn't find anything about the costs necessary to bring up a fab?
A project that addresses that issue is betrusted: https://betrusted.io/ Their plan for fab trust is not to bring up a fab,but to design for inspectability: https://bunnie.org/iris/
I happen to own a Precursor, and indeed used it for some experiments, but it's unfortunately limited by Xilinx Spartan-7 availability, which is one of the few FPGA's that have been reverse-engineered, and they probably don't make it anymore... Another one that has been RE'd is Lattice ECP5 but it's in the same category. I'm pretty sure you couldn't make 50 million devices like that. I know they've been looking into alternatives, but haven't caught up yet.
Their next one (https://baochip.com/) is going to be a SoC, piggy backed on another company's SoC. So not completely open source RTL, but enough to prove their technology on a larger scale. Bunnie's presentation of it is here: https://media.ccc.de/v/39c3-xous-a-pure-rust-rethink-of-the-... (25 minutes in)
Thanks for offering. Do you do analog design, and which market niche are you targeting: low cost per part or something else?
I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspective, because we are at most probably making several thousand of the chips. So the cost per chip can effectively range from 10-100$ at this scale, after yield losses. But the fixed costs of engineering and 'mask creation' for process nodes can range from 300k$ for nodes around 180 nm, to over 500k$ for 65nm, and above 1m$ for 28nm and below.
We can save money during initial prototyping, by creating a small test structure as small as 1mmm^2, which reduces the cost of a prototype run to 5k$ - 10k$. Some services that provide this are MOSIS [0] in the US, and Europractice [1] in the EU. But when we go to a full production run, there's no way to get around creating a 'full reticle' design, as image sensors have a physical dimension determined by focal plan size requirement of imaging application. For example, in digital camera, if a sensor is 'full frame' then it obviously has to be 36mm x 24mm, regardless of if the process node would have let you shrink it. And if you make a serious mistake, then you need to do another production run, which means you pay the 300k$ - 1m$ once again.
In terms of the circuit functionality, image sensors require a mixture of analog and digital design, but in this area, even many of the digital circuits are custom designed, rather than relying on foundry-provided 'standard cells' and an automatic place-and-route flow.
Oh thanks, this is really interesting. Is there a limit to how far you can scale down your node to build the full frame image sensor: is 180nm the largest feasible node?
Modern commercial image sensors are made in process nodes down to 28nm [0], and for visible light have pixels measuring 0.7-1.5 μm. At [0] there a diagram which gives a feel for what technology nodes are available and used for different applications. For example, RF ICs and power management ICs also typically use larger process nodes, and not just for reasons of cost. In fact a larger node, doesn't necessarily even mean older. For example, many technologies allowing better power handling capabilities in integrated circuits have come exclusively to larger nodes.
Regarding node sizes for image sensors, TSMC built a 28nm fab recently for Sony exclusively to make their latest sensors. There was actually a HN post about that a couple years ago [1]. Also, it's important to note that in many applications, the image sensor layer is now actually stacked, with a layer of DRAM (in 45 nm, for example) between, and a ISP (image signal processor) chip on the bottom made in a smaller digital process. You can see an image of that stack up here [2].
[0] https://image-sensors-world.blogspot.com/2020/08/tsmc-report... [1] https://news.ycombinator.com/item?id=24321804 [2] https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s...
This is great: thanks for all this.
More thank light bulbs. As you have correctly pointed it out, its a matter of economics: 180nm is CHEAP! So a lot more things become economically viable, think of all the weird specialized ASICs that used to be to expensive to build.
Not only that, but 180nm/130nm is the only option that is OpenSourced, as of now. Transistor Libraries for ICs (or, PDKs) have long been proprietary. I'm only aware of IHP and Sky130, which are actually banking on Fossi or Libre Silicon design.
True, someone needs to build that computer after all.
I've probably worked on 70 chips over the last 30 years.
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
Don’t worry we have those 80 hour weeks in software too. I can think of a few examples. For example with mobile App Store review time used to be kind of like that. You submitted your app waited a few business days and prayed there wasn’t an obscure rejection that lead to an appeal which could take even longer. Very stressful when you are cueing up a launch and press releases on a certain date. you had to make sure you were done a few weeks in advance to account for everything.
I don’t work much on apps anymore but I hear it’s somewhat better now.
Another big area is compliance, those processes can take forever.
Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 mask, instead of paying for a full new mask set?
If the change is under 1000 logic cells and no new flip flops then we do a it as an ECO. If there are tons of new flip flops we resynthesize and start over.
Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.
I've worked at one huge company where they planned 3 full base layer mask sets and 1-2 metal spins for each full base layer set. This was when doing a chip on a brand new process node where you couldn't always trust the models the fab gave you so you wanted more post silicon characterization to recalibrate models.
Wow, awesome thanks for the details! I have once or twice on projects added extra gates as fillers in some 28nm mixed-signal designs for metal layer re-work, but I had no idea that in larger digital teams there was also the practice of adding these types of individual transistor arrays. Super clever!
> The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.
Oh, this is fascinating.
The other alternative is that you sprinkle spare gates around the chip. If the chip is 10mm x 10mm then every 100 microns you put a group of cells that just have their inputs tied to 0 and the outputs go nowhere. You put in a good mix of flip flops, and combinational logic cells. Then when you need to do a metal ECO the RTL team says "We need 2 AND gates, 1 OR gate, 1 mux, and they are connected to these 5 cells." So you highlight those 5 cells and find the closest spare logic group and use those.
The ECOFILLER gate array style cells are easier to use.
Then during the DRC check process in Calibre we run a check to make sure that the base layers stayed the same and only the metal layers changed. Since we have 18 metal layers in a leading edge node hopefully only metal layers 1 to 3 changed for the metal ECO so you only have to pay to make new versions of that.
A full mask set in 3nm can be over $30 million. Just a new set of metal masks is around $20 million.
A full mask run takes about 4 months in the fab. Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers. Then when you do a metal respin they get those out of storage and save a month.
So you want to sprinkle the faster cell groups around, but the ecofiller gates are more flexible since they are everywhere by default ?
> Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers.
Oh, I had no idea that was a thing.
I've been doing this for 30 years.
Blocks are never 100% full. If it was then you would never be able to route the design. High utilization may be 70% but if a block has tons of IO then I've worked on blocks that are only 25% utilized. For various manufacturing and yield purposes the empty spaces need filler cells.
Sometimes we put in decoupling cap cells. But the ecofiller cells go in everywhere else.
About 25 years ago we were using spare gates that we had preplaced on the die.
About 5 years ago we started using spare gates preplaced and ALSO the ecofiller cells. The reason I was told was to save money because the ecofiller cells require some other mask layer to change. I think that was in the $500K range but it's still money.
In general I hate doing ECO's with the preplaced spare gates as it is manual and time consuming to find the best cells to use.
Incredible dive into something I’ve only dreamed of doing, this post is definitely one of my favorites. If the author is reading this, would love to know where you got those chairs!
> So when the opportunity arose to join an experimental shuttle using global foundries 180nm for FREE I jumped onto the opportunity and designed my own JTAG!
In case anyone wants a preview of what to expect.
> Because the official JTAG spec lives behind the impregnable IEEE paywall, a castle in which I am not permitted to set foot as a result of not having paid its lord my dues, the verification of the JTAG TAP was actually quite interesting.
> aka: For those not living in 2026, we have uncovered a new clue to the mystery of where all the low-power DRAM chips have suddenly vanished to!
I love the writing style!
A hugely entertaining blog post, despite subject matter that could easily result in very dry reading.
As someone who isn’t familiar with the deep details of the hardware side of the AI industry, I’m curious if these chips are “easy” to write AI software for, or if there is a big barrier. How significant is Nvidia’s moat on the software layer, which I often see talked about in articles, when people seem to be willing to adopt AI accelerators. And if AI accelerators can be adopted, why aren’t other competitors to Nvidia (AMD, Intel, etc) able to break in?
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Out of curiosity, does anyone know how many of the tools involved in the Tiny Tapeout project are available open source?
Especially in the project roadmap section..
The licences for proprietary EDA tools are very expensive it seems and most EDA people i talked to didn't really care for any open source tools - as their companies paid for the licenses.
You're right that most professional designers historically haven't cared about open source tooling. But this is starting to change, largely because of the recent existence of open PDKs and the creation of better open tools like OpenROAD. I am a PhD student working in chip design, and about 90% of my work is done using open tools. You can see an image of one chip here, for example.
You can do the entire project roadmap with entirely open source tools and all the tiny tapeout tools are open source.
some of my favorite projects from tiny tapeout:
https://tinytapeout.com/chips/tt05/tt_um_rejunity_sn76489
How to tell us you have a thing for sound generators, without telling us you have a thing for sound generators. Cool list !
I'm shocked that SRAMs would be considered a luxury item for open silicon. They're essential for building anything that would be commercially viable, since area is far from free.
As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will. SDF-annotated simulation actually shows data hazards, as well as transistor timings.
https://librelane.readthedocs.io/en/latest/usage/timing_clos...
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